Among the types of electrically alterable programmable memories in the prior art, there are "conventional" EEPROMs and "flash" EPROMs (which are also often referred to as flash EEPROMs). Conventional EEPROMs, because they utilize Fowler-Nordheim tunneling to program and erase, typically have a two transistor cell design. The first transistor has a stacked control gate and floating gate, and is programmed to a negative threshold voltage. The second transistor, usually called a select transistor, operates to access the first transistor.
Flash EPROMs provide an advantage over conventional EEPROMs in cell size. Unlike conventional EEPROMs, flash EPROMs are programmed using hot electron injection, and erased using Fowler-Nordheim tunneling. This results in a positive programmed threshold value for the stacked gate structure, eliminating the need for a select transistor. Thus, flash EEPROMs are typically manufactured with cell designs having only one transistor, providing for smaller cell sizes and allowing for denser memories.
A one transistor flash EPROM cell is set forth in cross section in FIG. 1. As shown in the figure, the cell 10 includes a silicon substrate 12 and a gate "stack" 14 having a layer of tunnel oxide 16, a floating gate 18 (typically polysilicon), an intergate dielectric 20, and a control gate 22 (also typically polysilicon). A source region 24 and a drain region 26 are formed within the substrate 12 on opposing sides of the gate stack 14, with both regions having portions extending underneath the floating gate 18. While conventional EEPROMs may be selectively erased in a byte-by-byte fashion, flash EPROMs cells are typically arranged with common drain diffusions and/or connections, requiring simultaneous erasing of all of the cells, or blocks of cells (often called pages).
In a typical flash EPROM cell fabrication process, following the formation of the gate stack, the source and drain regions are formed by ion implanting a dopant into the substrate, with the gate stack functioning as a mask. Following ion implantation, the wafer is typically heat treated, activating the implanted dopant, repairing lattice damage, and allowing the dopant to diffuse outward. Because ion implantation of the source region 24 is performed at an implantation angle of zero (or close to zero, depending on lattice structure) the dopant concentration decreases as the source region 24 extends underneath the gate stack 14.
The critical operating parameters of any flash EPROM cell are its program speed, erase speed, and read current. As mentioned previously, a programmed cell stores a number of electrons that have been injected via hot electron injection. During the erase operation of flash cell, a positive potential is applied between the source and the control gate, and electrons tunnel through the tunnel oxide to the source. A number of prior art teachings have addressed optimization of the program and/or erase operation of flash EPROMs.
For example, because a relatively large voltage (.about.12 volts) is introduced during erase operations, it is well-known to use a double-diffused source to prevent reverse breakdown of the source-substrate junction during programming.
U.S. Pat. No. 5,077,691 issued to Haddad et al., on Dec. 31, 1991, provides a flash EPROM design and erasing scheme that eliminates the need for a double diffused source by applying a relatively high negative voltage to the control gate and a relatively low positive voltage to the source (while placing the substrate at 0 volts).
U.S. Pat. No. 5,190,887 issued to Tang et at., on Mar. 2, 1993, discloses a method of fabricating a flash EPROM cell wherein large angle ion implantation is used to implant a significant number of ions into the drain region and the portion of the channel near the drain region. The large angle implanted ions are of the same conductivity type as the channel, and increase the channel doping adjacent to the drain regions. This allows for increased programming performance, and increased source and drain doping (of a conductivity type opposite to that of the substrate) for greater source-substrate breakdown voltages. While providing an improved channel concentration arrangement, Tang et al. does not provide a way to improve erase performance, except by increasing the source-drain implant.
U.S. Pat. No. 5,267,194 issued to Wen-Yueh Jang, on Nov. 11, 1993 discloses an EEPROM cell that includes a control gate having a reentrant profile. An adjacent floating gate is disposed between the control gate and the source, and include a protrusion that extends into the reentrant portion of the control gate. The reentrant profile and corresponding floating gate protrusion enhance erase operation. While providing for increased erase efficiency, the cell as taught by Jang is not a stacked structure, and requires a larger cell size.
U.S. Pat. No. 4,894,802 issued to Hsia et al., on Jan. 16, 1990 discloses a flash EPROM cell having a tunnel oxide window of decreased thickness between the drain and the floating gate for increased programming efficiency and improved program/erase endurance. As with the teachings of Jang, Hsia et al. presents a cell of relatively large size.